This invention relates to automatic place and route tools used to provide wiring patterns on semiconductor integrated circuits, and more particularly to a physical design tool that detects vias that may lead to yield and reliability problems and creates larger or redundant vias.
Quite often semiconductor manufacturers suffer lower yields and reliability problems due to via resistance introduced by vias of minimum area. In order to obtain dense designs, automatic place and route tools use minimum width and space wires. As such, vias created by these tools are of minimum area. These single minimum area vias can have increased resistance.
This results in yield problems for high performance circuits. This is especially true for Application Specific Integrated Circuits (ASIC) which have global wiring patterns that are needed to interconnect cells in the ASIC library and where a majority of the global chip wiring is accomplished by automatic wiring tools. Additionally, because testing, thermal cycling and burn-in do not accelerate detection of via resistance problems, minimum area vias often lead to more field returns. Finally, with the increasing performance and density of integrated circuits, the RC delay due to via resistance is becoming a larger factor in timing.
Of course, one solution to this problem is to simply have automatic wiring tools introduce redundant vias into the design. However, since many products like ASICs have complex wiring patterns, the automatic introduction would likely lead to larger die size and uncompetitive products. In other words, any yield and reliability benefit from universally using doubled or larger vias is offset by a larger, less productive chip die size.
A second solution, which is unfeasible for many modem designs, is the manual insertion of larger shapes after the wiring design is completed. Not only is this impracticable for complex designs, where the number of vias in a design are in the millions, but it also leads to inconsistent optimizations across a design.
A third solution, in use at International Business Machine Microelectronic's Division's circuit design centers, is to use shape processing-based tools to provide a post processing in program which adds vias and metal caps as flat shapes where feasible under the design rules for the process. There are problems with this approach, too. The processing time in using such an approach can be great. Secondly, the system algorithm must flatten any nested shapes which results in large data volumes. Thirdly, this approach does not provide the analysis capabilities you need in undertaking such tasks such as timing or electromigration analysis. Fourthly, the shapes based approach is more cumbersome to fit into the designer's methodology. As circuits increase in performance and complexity these factors become a much greater consideration.
Therefore, what is needed is a solution that minimizes additional critical metal, processes efficiently, works with design methodologies and tools, and allows for ease of engineering change.